HD64F2638F20J Datasheet, PDF (1446/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Notes: 1. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
2. RXI and ERI interrupt request cancellation can be performed by reading 1 from the
RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
3. The TDRE flag in SSR is fixed at 1.
4. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
6. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
7. When receive data including MPB = 0 is received, receive data transfer from RSR to
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,
is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR
is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
8. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
TDR0—Transmit Data Register 0
Bit
7
6
5
H'FF7B
4
3
SCI0, Smart Card Interface 0
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Store serial transmit data
Page 1396 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010