HD64F2638F20J Datasheet, PDF (892/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21B.14.1 Notes on Power-Down States
1. When the flash memory is in a power-down state, part or all of the internal power supply
circuitry is halted. Therefore, a power supply circuit stabilization period must be provided
when returning to normal operation. When the flash memory returns to its normal operating
state from a power-down state, bits STS2 to STS0 in SBYCR must be set to provide a wait
time of at least 20 µs (power supply stabilization time), even if an oscillation stabilization
period is not necessary.
2. In a power-down state, FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR cannot be
read from or written to.
21B.15 Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
programmer mode are summarized below.
Use the specified voltages and timing for programming and erasing: Applied voltages in
excess of the rating can permanently damage the device. Use a PROM programmer that supports
the Renesas microcomputer device type* with 256-kbyte and 512-kbyte on-chip flash memory.
Only use the specified socket adapter. Failure to observe these points may result in damage to the
device.
Note: * The H8S/2638 and H8S/2639 are Renesas Electronics microcomputer devices with 256
kbytes of on-chip flash memory. The H8S/2630 is a Renesas microcomputer device with
512 kbytes of on-chip flash memory (The H8S/2630 has 384 kbytes of PROM. The area
from H'60000 to H'7FFFF should be programmed as H'FF).
Powering on and off (see figures 21B-18 to 21B-20): Do not apply a high level to the FWE pin
until V_CC has stabilized. Also, drive the FWE pin low before turning off V_CC.
When applying or disconnecting V_CC power, fix the FWE pin low and place the flash memory in
the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
Page 842 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010