HD64F2638F20J Datasheet, PDF (704/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16.3.2 Initialization after Hardware Reset
After a hardware reset, the following initialization processing should be carried out:
• Clearing of IRR0 bit in interrupt register (IRR)
• Bit rate setting
• Mailbox transmit/receive settings
• Mailbox (RAM) initialization
• Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from
software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting
must be made each time a CAN node begins communication. The baud rate and bit timing settings
are made in the bit configuration register (BCR).
a. Note
BCR can be written to at all times, but should only be modified in configuration mode.
Settings should be made so that all CAN controllers connected to the CAN bus have the same
baud rate and bit width.
Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in
table 16-3.
Page 654 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010