HD64F2638F20J Datasheet, PDF (1359/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
PWBFR2A—PWM Buffer Register 2A
PWBFR2B—PWM Buffer Register 2B
PWBFR2C—PWM Buffer Register 2C
PWBFR2D—PWM Buffer Register 2D
H'FC18
H'FC1A
H'FC1C
H'FC1E
PWM2
PWM2
PWM2
PWM2
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
⎯ ⎯ ⎯ TDS ⎯ ⎯ DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
Read/Write ⎯ ⎯ ⎯ R/W ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Duty
Bits 9 to 0 compromise the data transferred to
bits 9 to 0 in PWDTR2
Transfer Destination Select
Selects the PWDTR2 register to which data is to be transferred
Register
TDS
Description
PWBFR2A
0
PWDTR2A selected
1
PWDTR2E selected
PWBFR2B
0
PWDTR2B selected
1
PWDTR2F selected
PWBFR2C
0
PWDTR2C selected
1
PWDTR2G selected
PWBFR2D
0
PWDTR2D selected
1
PWDTR2H selected
Note: When a PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or
PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or
PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H.
PHDDR—Port H Data Direction Register
H'FC20
Port
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1309 of 1458