HD64F2638F20J Datasheet, PDF (629/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Start
Initial settings
Read BBSY flag in ICCR
No
BBSY = 0?
Yes
Set MST = 1
and TRS = 1 (ICCR)
Write BBSY = 1
and SCP = 0 (ICCR)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Write transmit data to ICDR
Clear IRIC flag in ICCR
[1] Initial settings
[2] Determine status of SCL and SDA lines
[3] Set to master transmit mode
[4] Generate start condition
[5] Wait for start condition to be met
[6] Set 1st byte (slave address + R/W) transmit data
(Perform ICDR write and IRIC flag clear
operations continuously)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Read ACKB bit in ICSR
ACKB = 0?
No
Yes
No
Transmit mode?
Yes
Write transmit data to ICDR
Clear IRIC flag in ICCR
[7] Wait for end of 1 byte transmission
[8] Judge acknowledge signal from specified
slave device
Master receive mode
[9] Set transmit data for 2nd byte onward
(Perform ICDR write and IRIC flag clear
operations continuously)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Read ACKB bit in ICSR
No _{Transmit complete?}
(ACKB = 1?)
Yes
Clear IRIC flag in ICCR
Write BBSY = 0 and
SCP = 0 (ICCR)
End
[10] Wait for end of 1 byte transmission
[11] Judge end of transmission
[12] Generate stop condition.
Figure 15-7 Flowchart for Master Transmit Mode (Example)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 579 of 1458