HD64F2638F20J Datasheet, PDF (647/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.3.9 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15-20 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
System clock
period
Figure 15-20 Block Diagram of Noise Canceler
15.3.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 15.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 597 of 1458