HD64F2638F20J Datasheet, PDF (179/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 5 Interrupt Controller
5.4.5 Interrupt Response Times
The chip is capable of fast word transfer instruction to on-chip memory, and the program area is
provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5-9 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5-9 are explained in table 5-10.
Table 5-9 Interrupt Response Times
Normal Mode^*5
Advanced Mode
No. Execution Status
1 Interrupt priority determination^*1
INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1
3
3
3
3
2 Number of wait states until executing 1 to
1 to
1 to
1 to
instruction ends^*2
(19 + 2 · SI) (19 + 2 · SI) (19 + 2 · SI) (19 + 2 · SI)
3 PC, CCR, EXR stack save
2 · SK
3 · SK
2 · SK
3 · SK
4 Vector fetch
5 Instruction fetch^*3
6 Internal processing^*4
SI
2 · SI
2
SI
2 · SI
2
2·SI
2 · SI
2
2·SI
2 · SI
2
Total (using on-chip memory)
11 to 31 12 to 32
12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
5. Not implemented in the chip.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 129 of 1458