HD64F2638F20J Datasheet, PDF (246/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
8.2.6 DTC Transfer Count Register B (CRB)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: _{* * * * * * * * * * * * * * * *}
R/W
: ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
*: Undefined
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7 DTC Enable Registers (DTCER)
Bit
:
Initial value:
R/W
:
7
DTCE7
0
R/W
6
5
DTCE6 DTCE5
0
0
R/W R/W
4
3
2
DTCE4 DTCE3 DTCE2
0
0
0
R/W R/W R/W
1
0
DTCE1 DTCE0
0
0
R/W R/W
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG
with bits corresponding to the interrupt sources that can control enabling and disabling of DTC
activation. These bits enable or disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Page 196 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010