HD64F2638F20J Datasheet, PDF (18/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
21B.9.4 Erase-Verify
Mode
Figure 21B-13
Erase/Erase-Verify
Flowchart
Page
832
21B.13 Programmer 840
Mode
21B.14 Flash Memory 841
and Power-Down
States
Table 21B-14 Flash
Memory Operating
States
Revision (See Manual for Details)
Figure amended
Start
*1
Set SWE bit in FLMCR1
Wait (t_sswe) μs
*5
n=1
Set EBR1 or EBR2
*3 *4
Enable WDT
Set ESU bit in FLMCR1
Wait (t_sesu) μs
Set E bit in FLMCR1
Wait (t_se) ms
Clear E bit in FLMCR1
Wait (t_ce) μs
Clear ESU bit in FLMCR1
Wait (t_cesu) μs
Disable WDT
Set EV bit in FLMCR1
Wait (t_sev) μs
*5
Start of erase
*5
Erase halted
*5
*5
*5
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait (t_sevr) μs
*5
Increment
address
NG
Read verify data
Verify data = all 1s?
OK
Last address of block?
OK
Clear EV bit in FLMCR1
*2
NG
*5
Wait (t_cev) μs
NG
*4
All erase block erased?
OK
Clear SWE bit in FLMCR1
*5
Wait (t_cswe) μs
End of erasing
Clear EV bit in FLMCR1
*5
Wait (t_cev) μs
*5
n ≥ (N)?
OK
Clear SWE bit in FLMCR1
NG
*5
Wait (t_cswe) μs
Erase failure
Title amended and description replaced
Notes amended
Note: * Subclock functions (subactive mode, subsleep mode,
and watch mode) are available in the U-mask
and W-mask versions only. These functions cannot be
used with other versions.
Page xviii of l
REJ09B0103-0800 Rev. 8.00
May 28, 2010