HD64F2638F20J Datasheet, PDF (645/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.3.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 15-19 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I²C bus format, no wait)
SCL
7
8
9
1
SDA
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I²C bus format, wait inserted)
SCL
8
9
1
SDA
8
A
1
IRIC
User processing
Clear
IRIC
Clear Write to ICDR (transmit)
IRIC or read ICDR (receive)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Figure 15-19 IRIC Setting Timing and SCL Control
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 595 of 1458