HD64F2638F20J Datasheet, PDF (493/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
12.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated
when a TCNT overflow occurs.
12.5 Usage Notes
12.5.1 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 12-8 shows this operation.
TCNT write cycle
T₁
T₂
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12-8 Contention between TCNT Write and Increment
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 443 of 1458