HD64F2638F20J Datasheet, PDF (626/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
15.3 Operation
15.3.1 I²C Bus Data Format
The I²C bus interface has serial and I²C bus formats.
The I²C bus formats are addressing formats with an acknowledge bit. These are shown in figures
15-3 (a) and (b). The first frame following a start condition always consists of 8 bits.
The serial format is a non-addressing format with no acknowledge bit. Although start and stop
conditions must be issued, this format can be used as a synchronous serial format. This is shown in
figure 15-4.
Figure 15-5 shows the I²C bus timing.
The symbols used in figures 15-3 to 15-5 are explained in table 15-4.
(a) I²C bus format (FS = 0 or FSX = 0)
S
SLA
R/W A
DATA
1
7
11
n
1
A
1
m
A/A P
11
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
(b) I²C bus format (start condition retransmission, FS = 0 or FSX = 0)
S
SLA
R/W A
DATA
1
7
11
n1
A/A S
11
SLA
R/W A
7
11
DATA
n2
A/A P
11
1
m1
1
m2
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
Figure 15-3 I²C Bus Data Formats (I²C Bus Formats)
Page 576 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010