HD64F2638F20J Datasheet, PDF (962/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
22A.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
22A.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, or φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
22A.7 Subclock Oscillator
Connecting 32.768kHz Quartz Oscillator (U Mask, W Mask): To supply a clock to the
subclock divider, connect a 32.768kHz quartz oscillator, as shown in figure 22A-8. See section
22A.3.1, “Notes on Board Design” for notes on connecting quartz oscillators.
OSC1
OSC2
C1
C2
C1=C2=15pF (typ)
Figure 22A-8 Example Connection of 32.768kHz Quartz Oscillator
Figure 22A-9 shows the equivalence circuit for a 32.768kHz oscillator.
Ls
Cs
Rs
OSC1
OSC2
Co
Cs = 1.5 pF (typ.)
Rs = 14 kΩ (typ.)
fw = 32.768 kHz
Figure 22A-9 Equivalence Circuit for 32.768kHz Oscillator
Page 912 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010