HD64F2638F20J Datasheet, PDF (627/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
FS = 1 and FSX = 1
S
DATA
1
8
1
DATA
n
m
P
1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
Figure 15-4 I²C Bus Data Format (Serial Format)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA R/W A
DATA
A
DATA
A/A
P
Figure 15-5 I²C Bus Timing
Table 15-4 I²C Bus Data Format Symbols
Legend
S
SLA
R/W
A
DATA
P
Start condition. The master device drives SDA from high to low while SCL is high
Slave address, by which the master device selects a slave device
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
Stop condition. The master device drives SDA from low to high while SCL is high
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 577 of 1458