HD64F2638F20J Datasheet, PDF (594/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Smart Card Interface
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If data transfer by the DTC* by means of the TXI source is enabled, the next data can be
written to TDR automatically. When data is written to TDR by the DTC*, the TDRE bit is
automatically cleared to 0.
Note: * The DTC is not implemented in the H8S/2635 Group.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer
frame n + 1
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
TEND
FER/ERS
Transfer to TSR from TDR
[7]
[9]
[6]
[8]
Transfer to TSR
from TDR
Figure 14-12 Retransfer Operation in SCI Transmit Mode
Page 544 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010