HD64F2638F20J Datasheet, PDF (675/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.2.5 Transmit Wait Register (TXPR)
The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a
transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
TXPR
Bit: 15
14
13
12
11
10
9
8
TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
0
TXPR8
0
R/W
Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8):
These bits set a transmit wait for the corresponding mailboxes.
Bit y: TXPRx
0
1
Description
Transmit message idle state in corresponding mailbox
[Clearing condition]
(Initial value)
• Message transmission completion and cancellation completion
Transmit message transmit wait in corresponding mailbox (CAN bus
arbitration)
(x = 15 to 1, y = 15 to 9 and 7 to 0)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 625 of 1458