HD64F2638F20J Datasheet, PDF (32/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

5.6.3 Operation ............................................................................................................. 134
Section 6 PC Break Controller (PBC) ........................................................................... 137
6.1 Overview........................................................................................................................... 137
6.1.1 Features................................................................................................................ 137
6.1.2 Block Diagram..................................................................................................... 138
6.1.3 Register Configuration......................................................................................... 139
6.2 Register Descriptions ........................................................................................................ 139
6.2.1 Break Address Register A (BARA) ..................................................................... 139
6.2.2 Break Address Register B (BARB) ..................................................................... 140
6.2.3 Break Control Register A (BCRA) ...................................................................... 140
6.2.4 Break Control Register B (BCRB) ...................................................................... 142
6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 142
6.3 Operation .......................................................................................................................... 143
6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 143
6.3.2 PC Break Interrupt Due to Data Access............................................................... 144
6.3.3 Notes on PC Break Interrupt Handling ................................................................ 144
6.3.4 Operation in Transitions to Power-Down Modes ................................................ 145
6.3.5 PC Break Operation in Continuous Data Transfer............................................... 146
6.3.6 When Instruction Execution Is Delayed by One State......................................... 147
6.3.7 Additional Notes .................................................................................................. 148
Section 7 Bus Controller ................................................................................................... 149
7.1 Overview........................................................................................................................... 149
7.1.1 Features................................................................................................................ 149
7.1.2 Block Diagram..................................................................................................... 150
7.1.3 Pin Configuration................................................................................................. 151
7.1.4 Register Configuration......................................................................................... 151
7.2 Register Descriptions ........................................................................................................ 152
7.2.1 Bus Width Control Register (ABWCR)............................................................... 152
7.2.2 Access State Control Register (ASTCR) ............................................................. 153
7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 154
7.2.4 Bus Control Register H (BCRH) ......................................................................... 158
7.2.5 Bus Control Register L (BCRL) .......................................................................... 160
7.2.6 Pin Function Control Register (PFCR) ................................................................ 161
7.3 Overview of Bus Control .................................................................................................. 163
7.3.1 Area Partitioning.................................................................................................. 163
7.3.2 Bus Specifications ............................................................................................... 164
7.3.3 Memory Interfaces............................................................................................... 165
7.3.4 Interface Specifications for Each Area ................................................................ 166
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REJ09B0103-0800 Rev. 8.00
May 28, 2010