HD64F2638F20J Datasheet, PDF (1388/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TIOR3H—Timer I/O Control Register 3H
H'FE82
Bit
Initial value
Read/Write
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
TPU3
0
IOA0
0
R/W
TGR3A I/O Control
0 0 0 0 TGR3A is Output disabled
1 ^output
compare
1 0 _register
Initial output is 0
output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3A is Capture input
Input capture at rising edge
1 ^input
capture
1 * _register
source is
TIOCA3 pin
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT4 count-up/
source is channel count-down
4/count clock
*: Don't care
TGR3B I/O Control
0 0 0 0 TGR3B is Output disabled
1 ^output
Initial output is 0
1
compare
0 _register
output
1
0 output at compare match
1 output at compare match
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3B is Capture input
Input capture at rising edge
1 ^input
capture
1 * _register
source is
TIOCB3 pin
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT4 count-up/
source is channel count-down^*1
4/count clock
*: Don't care
Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
Page 1338 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010