HD64F2638F20J Datasheet, PDF (114/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
End of bus request
Bus request
Endroef^qbu_B^ues_u^s_s^t _re^quest
Program execution state
SLEEP
instruction
with
SSBY = 0
Bus-released state
Interrupt ^request
Sleep mode
SLEEP
instruction
with
SSBY = 1
Exception handling state
External interrupt request
Software standby mode
RES = High
Reset state ^*1
Reset state
STBY = High, RES = Low
Hardware standby mode^*2
Power-down state^*3
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See section 23A, 23B, Power-Down Modes.
Figure 2-15 State Transitions
2.8.2 Reset State
When the RES goes low, all current processing stops and the CPU enters the reset state. In reset
state all interrupts are disenabled.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer.
Page 64 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010