HD64F2638F20J Datasheet, PDF (56/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 1 Overview
1.2 Internal Block Diagram
Figure 1-1 (a) shows an internal block diagram of the H8S/2636.
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
VCL
MD2
MD1
MD0
OSC2*¹
OSC1*¹
EXTAL
XTAL
PLLCAP
STBY
RES
NMI
FWE*²
PF7/ φ
PF6/ AS
PF5/ RD
PF4/ HWR
PF3/ LWR/ADTRG/IRQ3
PF0/ IRQ2
PH0/ P W M 1 A
PH1/ P W M 1 B
PH2/ P W M 1 C
PH3/ P W M 1 D
PH4/ P W M 1 E
PH5/ P W M 1 F
PH6/ P W M 1 G
PH7/ P W M 1 H
PJ0/ P W M 2 A
PJ1/ P W M 2 B
PJ2/ P W M 2 C
PJ3/ P W M 2 D
PJ4/ P W M 2 E
PJ5/ P W M 2 F
PJ6/ P W M 2 G
PJ7/ P W M 2 H
Port D
Port E
H8S/2600 CPU
PLL
Interrupt controller
PC break controller
DTC
ROM
(mask ROM,
flash memory)
RAM
TPU
PPG
WDT × 2 channels
SCI × 3 channels
Motor control PWM timer
D/A converter
A/D converter
HCAN × 2 channels
Port 1
Port 4
PA3 / A19/SCK2
PA2 / A18/RxD2
PA1 / A17/TxD2
PA0 / A16
PB7 / A15/TIOCB5
PB6 / A14/TIOCA5
PB5 / A13/TIOCB4
PB4 / A12/TIOCA4
PB3 / A11/TIOCD3
PB2 / A10/TIOCC3
PB1 / A9/TIOCB3
PB0 / A8/TIOCA3
PC7 / A7
PC6 / A6
PC5 / A5
PC4 / A4
PC3 / A3
PC2 / A2
PC1 / A1
PC0 / A0
P35 / SCK1/IRQ5
P34 / RxD1
P33 / TxD1
P32 / SCK0/IRQ4
P31 / RxD0
P30 / TxD0
P93 / AN11
P92 / AN10
P91 / AN9
P90 / AN8
Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
2. The FWE pin only applies to the flash memory version.
The FWE pin is a NC pin in the mask ROM versions.
In the mask ROM version, the FWE pin must be left open or be connected to Vss.
Figure 1-1 (a) Internal Block Diagram of H8S/2636
Page 6 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010