HD64F2638F20J Datasheet, PDF (1165/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix A Instruction Set
Branch
Byte Word
Instruction Address Stack
Data Data Internal
Fetch
Read Operation Access Access Operation
Instruction Mnemonic
I
J
K
L
M
N
XOR
XOR.B #xx:8,Rd
1
XOR.B Rs,Rd
1
XOR.W #xx:16,Rd
2
XOR.W Rs,Rd
1
XOR.L #xx:32,ERd
3
XOR.L ERs,ERd
2
XORC
XORC #xx:8,CCR
1
XORC #xx:8,EXR
2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.
2. When n bytes of data are transferred.
3. An internal operation may require between 0 and 3 additional states, depending on the
preceding instruction.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1115 of 1458