HD64F2638F20J Datasheet, PDF (182/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
5.5.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W
R4,R4
BNE
L1
5.5.5 IRQ Interrupts
When operating by clock input, acceptance of input to an IRQ pin is synchronized with the clock.
In software standby mode, the input is accepted asynchronously. For details on the input
conditions, see section 24.5.2, Control Signal Timing.
5.5.6 Notes on Use of NMI Interrupt
When the system is operating normally under conditions conforming to the specified electrical
properties, exception processing by the on-chip interrupt controller linked to the CPU is used to
execute the NMI interrupt. When operation is not normal (runaway status) due to a software
problem or abnormal input to one of the LSI’s pins, no operations can be guaranteed, including the
NMI interrupt. In such cases it is possible to cause the LSI to return to normal program execution
by applying an external reset.
Page 132 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010