HD64F2638F20J Datasheet, PDF (784/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Motor Control PWM Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
PWCYR2
PWBFR2A
PWDTR2A
PWDTR2E
TDS (PWBFR2A) = 0 TDS (PWBFR2A) = 1 TDS (PWBFR2A) = 0
PWM2A
PWM2B
Figure 19-11 PWM Channel 2 Operation
Next Frame: When a compare match occurs between PWCNT2 and PWCYR2, data is transferred
from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F,
from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or
PWDTR2H, according to the value of the TDS bit. PWCNT2 is reset and starts counting up from
H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be
requested or the DTC can be activated.
Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A
to PWDTR2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR2 is
set to 1).
Page 734 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010