HD64F2638F20J Datasheet, PDF (1389/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
TIOR3L—Timer I/O Control Register 3L
Bit
Initial value
Read/Write
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
H'FE83
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
TPU3
0
IOC0
0
R/W
TGR3C I/O Control
0 0 0 0 TGR3C is Output disabled
1 ^output
Initial output is 0 0 output at compare match
1
0
compare
register*¹
output
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3C is Capture input
Input capture at rising edge
1 ^input
source is
capture TIOCC3 pin
1 * _register*1
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT4 count-up/
source is channel count-down
4/count clock
*: Don't care
Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
TGR3D I/O Control
00
0 0 TGR3D is Output disabled
1 ^output
Initial output is 0
1
0
compare
register*²
output
1
0 output at compare match
1 output at compare match
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3D is Capture input Input capture at rising edge
1 ^input
source is
capture TIOCD3 pin
1 * _register*2
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT4 count-up/
source is channel count-down*¹
4/count clock
*: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1339 of 1458