HD64F2638F20J Datasheet, PDF (630/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write
operations, is described below.
[1] Perform initial settings as described in section 15.3.2, Initial Setting.
[2] Read the BBSY flag in ICCR to confirm that the bus is free.
[3] Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode.
[4] Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
[5] The IRIC and IRTR flags are set to 1 when the start condition is generated. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU.
[6] After the start condition is detected, write the data (slave address + R/W) to ICDR. With the
I²C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data
following the start condition indicates the 7-bit slave address and transmit/receive direction
(R/W). Next, clear the IRIC flag to 0 to indicate the end of the transfer. Continue
successively writing to ICDR and clearing the IRIC flag to ensure that processing of other
interrupts does not intervene. If the time required to transmit one byte of data elapses by the
time the IRIC flag is cleared, it will not be possible to determine the end of the transmission.
The master device sequentially sends the transmit clock and the data written to ICDR. The
selected slave device (i.e., the slave device with the matching slave address) drives SDA low
at the 9th transmit clock pulse and returns an acknowledge signal.
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit in ICSR to confirm that its value is 0. If the slave device has not returned
an acknowledge signal and the value of ACKB is 1, perform the transmit end processing
described in step [12] and then recommence the transmit operation from the beginning.
[9] Write the transmit data to ICDR. Next, clear the IRIC flag to 0 to indicate the end of the
transfer. Then continue successively writing to ICDR and clearing the IRIC flag as described
in step [6]. Transmission of the next frame is synchronized with the internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge
signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal
and the value of ACKB is 1, perform the transmit end processing described in step [12].
[12] Clear the IRIC flag to 0. Write 0 to the ACKE bit in ICCR and clear the received ACKB bit
to 0.
Page 580 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010