HD64F2638F20J Datasheet, PDF (158/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
5.2 Register Descriptions
Note: The H8S/2635 Group is not equipped with a DTC, a PC brake controller, or an HCAN1.
5.2.1 System Control Register (SYSCR)
Bit
:
Initial value :
R/W
:
7
MACS
0
R/W
6
5
4
3
2
⎯ INTM1 INTM0 NMIEG ⎯
0
0
0
0
0
⎯
R/W R/W R/W R/W
1
0
⎯ RAME
0
1
⎯
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt
Control Mode
0
—
2
—
Description
Interrupts are controlled by I bit
(Initial value)
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
(Initial value)
Page 108 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010