HD64F2638F20J Datasheet, PDF (763/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 19 Motor Control PWM Timer
Section 19 Motor Control PWM Timer
Note: The H8S/2635 Group is not equipped with a DTC.
19.1 Overview
The chip has an on-chip motor control PWM (pulse width modulator) with a maximum capability
of 16 pulse outputs.
19.1.1 Features
Features of the motor control PWM are given below.
• Maximum of 16 pulse outputs
⎯ Two 10-bit PWM channels, each with eight outputs.
⎯ Each channel is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR).
⎯ Duty and output polarity can be set for each output.
• Buffered duty registers
⎯ Duty registers (PWDTR) are provided with buffer registers (PWBFR), with data
transferred automatically every cycle.
⎯ Channel 1 has four duty registers and four buffer registers.
⎯ Channel 2 has eight duty registers and four buffer registers.
• 0% to 100% duty
⎯ A duty cycle of 0% to 100% can be set by means of a duty register setting.
• Five operating clocks
⎯ There is a choice of five operating clocks (φ, φ/2, φ/4, φ/8, φ/16).
• High-speed access via internal 16-bit-bus
⎯ High-speed access is possible via a 16-bit bus interface.
• Two interrupt sources
⎯ An interrupt can be requested independently for each channel by a cycle register compare
match.
• Automatic transfer of register data
⎯ Block transfer and one-word data transfer are possible by activating the data transfer
controller (DTC).
• Module stop mode
⎯ As the initial setting, PWM operation is halted. Register access is enabled by clearing
module stop mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 713 of 1458