HD64F2638F20J Datasheet, PDF (189/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 6 PC Break Controller (PBC)
6.1.3 Register Configuration
Table 6-1 shows the PC break controller registers.
Table 6-1 PC Break Controller Registers
Name
Abbreviation R/W
Break address register A
BARA
R/W
Break address register B
Break control register A
Break control register B
BARB
BCRA
BCRB
R/W
R/(W)^*2
R/(W)^*2
Module stop control register C
MSTPCRC
R/W
Notes: 1. Lower 16 bits of the address.
2. Only a 0 may be written to this bit to clear the flag.
Initial Value
Reset
H'XX000000
H'XX000000
H'00
H'00
H'FF
Address^*1
H'FE00
H'FE04
H'FE08
H'FE09
H'FDEA
6.2 Register Descriptions
6.2.1 Break Address Register A (BARA)
Bit
31 ^{. . .} 24 23 22 21 20 19 18 17 16 ^{. . .} 7 6 5 4 3 2 1 0
⎯ ^{. . .} ⎯ ^{BAA BAA BAA BAA BAA BAA BAA BAA . . . BAA BAA BAA BAA BAA BAA BAA BAA}
23 22 21 20 19 18 17 16
7 6 543 2 10
Initial value _Unde- . . . _{Unde- 0 0 0 0 0 0 0 0} . . . _{0 0 0 0 0 0 0 0}
fined
fined
Read/Write ⎯ ^{. . .} ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ^{. . .} R/W R/W R/W R/W R/W R/W R/W R/W
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC
break address.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 139 of 1458