HD64F2638F20J Datasheet, PDF (266/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Table 8-9 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution Vector read
SI
status
Register
SJ
information
read/write
Byte data read SK
Word data read SK
Byte data write SL
Word data write SL
Internal operation SM
On- On-
Chip Chip On-Chip I/O
RAM ROM Registers External Devices
32 16 8
16 8 8
16
1
1
2
223
2
—1
— — 4 6 + 2m 2
1
— — ———
—
16
3
3+m
—
1
1
2
2 2 3+m 2 3+m
1
1
4
2 4 6 + 2m 2 3 + m
1
1
2
2 2 3+m 2 3+m
1
1
4
2 4 6 + 2m 2 3 + m
1
1
1
111
11
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · (S_I + 1) + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 14 states. The time from activation to the end of the data write is 11 states.
Page 216 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010