HD64F2638F20J Datasheet, PDF (870/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Automatic SCI Bit Rate Adjustment
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more bits)
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800,
9,600 or 19,200 bps to operate the SCI properly.
Table 21B-10 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 21B-10 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
Is Possible
Host Bit Rate
System Clock Frequency for which Automatic Adjustment
of LSI Bit Rate Is Possible
4,800 bps
4 to 20 MHz
9,600 bps
8 to 20 MHz
19,200 bps
16 to 20 MHz
Note: The system clock frequency used in boot mode is generated by an external crystal oscillator
element. PLL frequency multiplication is not used.
Page 820 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010