HD64F2638F20J Datasheet, PDF (234/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
(3) Relationship between Chip Select (CS^*) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An
example is shown in figure 7-17.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Note: * The CS signal is generated externally rather than inside the LSI device.
φ
Address bus
CS* (area A)
CS* (area B)
RD
HWR
Data bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS* (area A)
CS* (area B)
RD
HWR
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Long output
floating time
(a) Idle cycle not inserted
(ICIS0 = 0)
Data
collision
(b) Idle cycle inserted
(Initial value ICIS0 = 1)
Note: * The CS signal is generated externally rather than inside the LSI device.
Figure 7-17 Relationship between Chip Select (CS)^* and Read (RD)
Page 184 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010