HD64F2638F20J Datasheet, PDF (687/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.2.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that
enable or disable requests by individual interrupt sources.
IMR
Bit: 15
14
13
12
11
10
9
8
IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1
—
Initial value: 1
1
1
1
1
1
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
—
—
— IMR12 —
—
IMR9 IMR8
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R/W
R
R
R/W R/W
Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables
overload frame/bus off recovery interrupt requests.
Bit 15: IMR7
0
1
Description
Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7
enabled
Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7
disabled
(Initial value)
Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused
by the transmit error counter.
Bit 14: IMR6
0
1
Description
Bus off interrupt request (ERS0) to CPU by IRR6 enabled
Bus off interrupt request (ERS0) to CPU by IRR6 disabled
(Initial value)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 637 of 1458