HD64F2638F20J Datasheet, PDF (39/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)........................... 545
15.1 Overview........................................................................................................................... 545
15.1.1 Features................................................................................................................ 545
15.1.2 Block Diagram..................................................................................................... 546
15.1.3 Input/Output Pins ................................................................................................. 548
15.1.4 Register Configuration......................................................................................... 549
15.2 Register Descriptions ........................................................................................................ 550
15.2.1 I²C Bus Data Register (ICDR) ............................................................................. 550
15.2.2 Slave Address Register (SAR) ............................................................................. 553
15.2.3 Second Slave Address Register (SARX) ............................................................. 554
15.2.4 I²C Bus Mode Register (ICMR)........................................................................... 555
15.2.5 I²C Bus Control Register (ICCR)......................................................................... 559
15.2.6 I²C Bus Status Register (ICSR) ........................................................................... 567
15.2.7 Serial Control Register X (SCRX)....................................................................... 573
15.2.8 DDC Switch Register (DDCSWR) ...................................................................... 574
15.2.9 Module Stop Control Register B (MSTPCRB).................................................... 575
15.3 Operation .......................................................................................................................... 576
15.3.1 I²C Bus Data Format............................................................................................ 576
15.3.2 Initial Setting........................................................................................................ 578
15.3.3 Master Transmit Operation .................................................................................. 578
15.3.4 Master Receive Operation.................................................................................... 582
15.3.5 Slave Receive Operation...................................................................................... 587
15.3.6 Slave Transmit Operation .................................................................................... 592
15.3.7 IRIC Setting Timing and SCL Control ................................................................ 595
15.3.8 Operation Using the DTC .................................................................................... 596
15.3.9 Noise Canceler ..................................................................................................... 597
15.3.10 Initialization of Internal State .............................................................................. 597
15.4 Usage Notes ...................................................................................................................... 599
Section 16 Controller Area Network (HCAN)............................................................ 611
16.1 Overview........................................................................................................................... 611
16.1.1 Features................................................................................................................ 611
16.1.2 Block Diagram..................................................................................................... 613
16.1.3 Pin Configuration................................................................................................. 614
16.1.4 Register Configuration......................................................................................... 615
16.2 Register Descriptions ........................................................................................................ 619
16.2.1 Master Control Register (MCR) .......................................................................... 619
16.2.2 General Status Register (GSR) ............................................................................ 620
16.2.3 Bit Configuration Register (BCR) ....................................................................... 622
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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