HD64F2638F20J Datasheet, PDF (836/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21A.12 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI interrupt is disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
mode*¹, to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*², possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI interrupt, must
therefore be restricted inside and outside the MCU when programming or erasing flash memory.
NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in
FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Page 786 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010