HD64F2638F20J Datasheet, PDF (1362/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
DDCSWR—DDC Switch Register
H'FDB5
IIC
Bit
:
Initial value :
R/W
:
7
⎯
0
R/(W)*¹
6
5
⎯
⎯
0
0
R/(W)*¹ R/(W)*¹
4
⎯
0
R/(W)*¹
3
CLR3
1
W*²
2
CLR2
1
W*²
1
CLR1
1
W*²
0
CLR0
1
W*²
Reserved bit
IIC clear 3 to 0
CLR3 CLR2 CLR1 CLR0
0
0
⎯ ⎯ Setting prohibited
1
0 0 Setting prohibited
1 IIC0 internal latch cleared
1 0 IIC1 internal latch cleared
1 IIC0 and IIC1 internal latches cleared
1
⎯
⎯ ⎯ Invalid setting
Notes: This register is valid only when an I²C bus interface has been added as an H8S/2638,
H8S/2639, and H8S/2630 option.
1. Should always be written with 0.
2. Always read as 1.
Page 1312 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010