HD64F2638F20J Datasheet, PDF (967/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 22B Clock Pulse Generator
(H8S/2639 Group, H8S/2635 Group)
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
0
1
Description
Specified multiplication factor is valid after transition to software standby mode,
watch mode, and subactive mode
(Initial value)
Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master is in high-speed mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
—
(Initial value)
22B.2.2 Low-Power Control Register (LPWRCR)
Bit
:7
6
5
4
3
2
DTON LSON NESEL SUBSTP RFCUT ⎯
Initial value : 0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
1
STC1
0
R/W
0
STC0
0
R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The
following pertains to bits 1 and 0. For details of the other bits, see section 23B.2.3, Low Power
Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby
mode. It is not initialized in software standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 917 of 1458