HD64F2638F20J Datasheet, PDF (483/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
WDT1 TCSR
Bit 4
PSS
Description
0
The TCNT counts frequency-division clock pulses of the φ based
prescaler (PSM)
(Initial value)
1
The TCNT counts frequency-division clock pulses of the φ SUB^*-based prescaler
(PSS)
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available only in
the U-mask and W-mask versions, but are not available in the other versions.
WDT0 TCSR Bit 3—Reserved: A read operation on this bit always causes a 1 to be read out.
Every write operation on this bit is invalidated.
WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
Bit 3
RST/NMI
0
1
Description
NMI request
Internal reset request
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ) or subclock* (φSUB), for input to TCNT.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions, and in them the PSS bit is
reserved. Only 0 should be written to this bit.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 433 of 1458