HD64F2638F20J Datasheet, PDF (14/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
Page
16.2.20 Module Stop 650
Control Register C
(MSTPCRC)
Bit 2—Module Stop
(MSTPC2)*:
16.3.2 Initialization 655
after Hardware Reset
Table 16-3 BCR
Register Value Setting
Ranges
Table 16-4 Setting 657
Range for TSEG1 and
TSEG2 in BCR
16.3.8 DTC Interface* 675
17.6 Usage Notes 700
Figure 17-7 Example
of Analog Input
Protection Circuit
Revision (See Manual for Details)
Note amended
Note: * The MSTPC2 is not available and is reserved in the
H8S/2635 Group.
Table amended
Name
Time segment 1
Time segment 2
Baud rate prescaler
Sample point
Synchronization jump width
Abbreviation
TSEG1
TSEG2
BRP
SAM
SJW
Min. Value
B'0011
B'001
B'000000
B'0
B'00
Max. Value
B'1111
B'111
B'111111
B'1
B'11
Note amended
Notes: The time quanta value for TSEG1 and TSEG2 is the
TSEG value + 1.
* Only a value other than BRP[13:8] = B'000000 can
be set.
Note amended
Note: * The DTC is not implemented in the H8S/2635 Group.
Figure amended
*1
*1
Rin* ²
100Ω
0.1 μF
AVCC
Vref
AN0 to AN11
AVSS
18.3 Operation
711
Figure 18-2 D/A
Conversion (Example)
Figure amended
DADR0
write cycle
DACR
write cycle
φ
Address
DADR0
Conversion data (1)
DADR0
write cycle
DACR
write cycle
Conversion data (2)
Page xiv of l
REJ09B0103-0800 Rev. 8.00
May 28, 2010