HD64F2638F20J Datasheet, PDF (190/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
6.2.2 Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3 Break Control Register A (BCRA)
Bit
Initial value
Read/Write
7
CMFA
0
R/(W)*
6
5
4
3
2
1
0
CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA
0
0
0
R/W R/W R/W
0
0
0
0
R/W R/W R/W R/W
Note: * Only a 0 may be written to this bit to clear the flag.
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
0
1
Description
[Clearing condition]
• When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
• When a condition set for channel A is satisfied
(Initial value)
Page 140 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010