HD64F2638F20J Datasheet, PDF (1447/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
H'FF7C
H'FF84
H'FF8C
SCI0
SCI1
SCI2
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multi-processor
bit is transmitted
1 Data with a 1 multi-processor
bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
• When data with a 0 multiprocessor
bit is received*⁷
Transmit End
1 [Setting condition]
• When data with a 1 multiprocessor
bit is received
0 [Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Parity Error
0 [Clearing condition]
• When 0 is written in PER after reading PER = 1*⁵
1 [Setting condition]
• When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR*⁶
Framing Error
0 [Clearing condition]
• When 0 is written in FER after reading FER = 1*³
1 [Setting condition]
• When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0*⁴
Overrun Error
0 [Clearing condition]
• When 0 is written in ORER after reading ORER = 1*¹
1 [Setting condition]
• When the next serial reception is completed while RDRF = 1*²
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
• When serial reception ends normally and receive data is transferred from RSR to RDR
Transmit Data Register Empty
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
0 [Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1397 of 1458