HD64F2638F20J Datasheet, PDF (1012/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0, MSTPCRD Bits 7 and 6—Module Stop
(MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and
MSTPD6): These bits specify module stop mode. See table 23B-5 for the method of selecting the
on-chip peripheral functions.
MSTPCRA/MSTPCRB/
MSTPCRC Bits 7 to 0,
MSTPCRD Bits 7 and 6
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0,
MSTPC7 to MSTPC0,
MSTPD7 and MSTPD6 Description
0
Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
1
Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0,
MSTPC7–0, and MSTPC7, 6)
23B.3 Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in
LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an
interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and
TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software
standby mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Page 962 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010