HD64F2638F20J Datasheet, PDF (650/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• The I²C bus interface specification for the SCL rise time t_sr is under 1000 ns (300 ns for high-
speed mode). In master mode, the I²C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t_sr (the time for SCL to go from low to V_IH) exceeds
the time determined by the input clock of the I²C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
15-7.
Table 15-7 Permissible SCL Rise Time (t_Sr) Values
tcyc
IICX Indication
0 7.5 tcyc Standard
mode
High-speed
mode
1 17.5 tcyc Standard
mode
High-speed
mode
Time Indication
I²C Bus
Specification φ =
(Max.)
5 MHz
φ=
8 MHz
1000 ns
1000 ns 937 ns
300 ns
300 ns 300 ns
1000 ns
1000 ns 1000 ns
300 ns
300 ns 300 ns
φ=
10 MHz
750 ns
300 ns
1000 ns
300 ns
φ=
φ=
16 MHz 20 MHz
468 ns 375 ns
300 ns 300 ns
1000 ns 875 ns
300 ns 300 ns
• The I²C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I²C bus interface SCL and SDA output timing is prescribed by t_Scyc and t_cyc, as
shown in table 15-6. However, because of the rise and fall times, the I²C bus interface
specifications may not be satisfied at the maximum transfer rate. Table 15-8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t_BUFO fails to meet the I²C bus interface specifications at any frequency. The solution is either
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I²C bus.
t_SCLLO in high-speed mode and t_STASO in standard mode fail to satisfy the I²C bus interface
specifications for worst-case calculations of t_Sr/t_Sf. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I²C
bus.
Page 600 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010