HD64F2638F20J Datasheet, PDF (485/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
WDT1 Input Clock Select
Bit 4 Bit 2
PSS^*2 CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
Clock
Overflow Period*¹ (where φ = 20 MHz)
(where φSUB*² = 32.768 kHz)
0
0
0
0
φ/2 (initial value) 25.6 µs
1
φ/64
819.2 µs
1
0
φ/128
1.6 ms
1
φ/512
6.6 ms
1
0
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
1
0
φ/32768
419.4 ms
0
1
1
1
φ/131072
1.68 s
1
0
0
0
φSUB/2^*2
15.6 ms
1
φSUB/4^*2
31.3 ms
1
0
φSUB/8^*2
62.5 ms
1
φSUB/16^*2
125 ms
1
0
0
φSUB/32^*2
250 ms
1
φSUB/64^*2
500 ms
1
0
φSUB/128^*2
1s
1
φSUB/256^*2
2s
Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in
the U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions, therefore PSS bit is reserved.
0 should be written when writing.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 435 of 1458