HD64F2638F20J Datasheet, PDF (863/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
21B.7.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically
cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory erase block configuration is shown in table 21B-7.
Bit: 7
6
5
4
3
2
1
0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
21B.7.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even
though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2
combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and
EBR2 to be automatically cleared to 0. On the H8S/2638 and H8S/2639 bits 7 to 4 are reserved,
and on the H8S/2630 bits 7 and 6 are reserved. Only 0 may be written to these reserved bits. When
on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory erase block configuration is shown in table 21B-7.
Bit: 7
—
6
5
4
3
2
1
0
—
EB13^* EB12^* EB11 EB10 EB9
EB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0
may be written to them.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 813 of 1458