HD64F2638F20J Datasheet, PDF (242/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
8.2 Register Descriptions
8.2.1 DTC Mode Register A (MRA)
Bit
:
Initial value :
7
SM1
*
6
SM0
*
5
DM1
*
R/W
:
⎯
⎯
⎯
4
DM0
*
⎯
3
MD1
*
⎯
2
MD0
*
⎯
1
0
DTS
Sz
*
*
⎯
⎯
*: Undefined
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bit 6
SM0
—
0
1
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Bit 4
DM0
—
0
1
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Page 192 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010