HD64F2638F20J Datasheet, PDF (171/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Table 5-5 Interrupt Control Modes
Interrupt
SYSCR _{Priority Setting}
Control Mode INTM1 INTM0 Registers
0
0
0
—
—
1
—
2
1
0
IPR
—
1
—
Section 5 Interrupt Controller
Interrupt
Mask Bits Description
I
Interrupt mask control is
performed by the I bit.
—
Setting prohibited
I2 to I0
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set
with IPR.
—
Setting prohibited
Figure 5-4 shows a block diagram of the priority decision circuit.
Interrupt
control
mode 0 I
Interrupt source
Interrupt
acceptance
control
8-level
mask control
Default priority
determination
Vector number
I2 to I0
IPR
Interrupt control mode 2
Figure 5-4 Block Diagram of Interrupt Control Operation
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 121 of 1458