HD64F2638F20J Datasheet, PDF (1445/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
SCR0—Serial Control Register 0
SCR1—Serial Control Register 1
SCR2—Serial Control Register 2
Bit
7
6
5
TIE
RIE
TE
Initial value
0
0
0
Read/Write R/W
R/W
R/W
H'FF7A
H'FF82
H'FF8A
4
3
RE MPIE
0
0
R/W R/W
Smart Card Interface 0
Smart Card Interface 1
Smart Card Interface 2
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
Transmit Interrupt Enable
0 Transmit-data-empty interrupt
(TXI) request disabled*¹
1 Transmit-data-empty interrupt
(TXI) request enabled
Receive Interrupt Enable
0 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled*²
1 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
Clock Enable 1 and 0
SCMR SMR SCR Setting
SCK Pin Function
SMIF C/A, GM CKE1 CKE0
0
See the SCI
1
0
0
0 Operates as port I/O pin
1 Outputs clock as SCK
output pin
1
0 Operates as SCK output
pin, with output fixed low
1 Outputs clock as SCK
output pin
1
1 Operates as SCK output
pin, with output fixed high
0 Outputs clock as SCK
output pin
Transmit End Interrupt Enable
0 Transmit-end interrupt (TEI) request disabled*⁸
1 Transmit-end interrupt (TEI) request enabled*⁸
Multiprocessor Interrupt Enable
0 Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled*⁷
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Receive Enable
0 Reception disabled*⁵
1 Reception enabled*⁶
Transmit Enable
0 Transmission disabled*³
1 Transmission enabled*⁴
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1395 of 1458