HD64F2638F20J Datasheet, PDF (463/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 11 Programmable Pulse Generator (PPG)
11.3 Operation
11.3.1 Overview
PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this
state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating
conditions.
DDR
NDER
Q
Output trigger signal
Pulse output pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 11-2 PPG Output Operation
Table 11-3 PPG Operating Conditions
NDER
0
1
DDR
0
1
0
1
Pin Function
Generic input port
Generic output port
Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the
next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 413 of 1458