HD64F2638F20J Datasheet, PDF (936/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21C ROM
(H8S/2635 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Start
*1
Set SWE bit in FLMCR1
Wait (t_sswe) μs
n=1
Set EBR1 or EBR2
*5
*3 *4
Enable WDT
Set ESU bit in FLMCR1
Wait (t_sesu) μs
Set E bit in FLMCR1
Wait (t_se) ms
Clear E bit in FLMCR1
Wait (t_ce) μs
Clear ESU bit in FLMCR1
Wait (t_cesu) μs
Disable WDT
*5
Start of erase
*5
Erase halted
*5
*5
Set EV bit in FLMCR1
Wait (t_sev) μs
*5
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait (t_sevr) μs
*5
Increment
address
NG
Read verify data
Verify data = all 1s?
OK
Last address of block?
OK
Clear EV bit in FLMCR1
*2
NG
*5
Wait (t_cev) μs
NG
*4
All erase block erased?
OK
Clear SWE bit in FLMCR1
*5
Wait (t_cswe) μs
End of erasing
Clear EV bit in FLMCR1
*5
Wait (t_cev) μs
*5
n ≥ (N)?
OK
Clear SWE bit in FLMCR1
NG
*5
Wait (t_cswe) μs
Erase failure
Notes: 1.
2.
3.
4.
5.
Prewriting (setting erase block data to all 0s) is not necessary.
Verify data is read in 16-bit (word) units.
Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
The wait times and the value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics.
Figure 21C-13 Erase/Erase-Verify Flowchart
Page 886 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010