HD64F2638F20J Datasheet, PDF (1016/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
23B.5.2 Usage Notes
Note: The DTC is not implemented in the H8S/2635 Group.
DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6
bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when
the respective module is not activated.
For details, refer to section 8, Data Transfer Controller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
23B.6 Software Standby Mode
23B.6.1 Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all stop*. However, the contents
of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, Motor control PWM, HCAN and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state.
In this mode the oscillator stops*, and therefore power dissipation is significantly reduced.
Note: * The subclock (φSUB) operates if the SUBSTP bit in LPWRCR is set to 0.
Page 966 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010